Job Description

Overview

Senior System Validation Engineer SerDes/Ethernet (PAM4) San Jose, CA

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the companys COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at .

Responsibilities

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers system requirements in the highest regard and is solely responsible for certifying a products conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs solutions.

Education and Experience

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelors is required, and a Masters is preferred.
• ?6 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

EEO Statement

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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